Review paper on stacking and interconnects for CMOS image sensors

In an ASME J. Electron. Packag. paper titled “Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors” Mei-Chien Lu writes:

Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS image sensors (CIS) for different functions such as visible light detection, single photon avalanche photodiode (SPAD) for low light detection, rolling shutter, and global shutter, and depth sensing and light detection and ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultrahigh-density interconnect manufacturability is also highlighted.

Schematics of an imaging pixel array, circuit blocks and a typical 4 T-APS pixel electronics

Exemplary schematics of front side illuminated sensors (FSI-CIS) and back side illuminated sensors (BSI-CIS)

Schematics of ceramic leadless chip carrier ceramic image sensor package at the top and imaging ball grid array image sensor package at the bottom

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